Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit.
Semiconductor dies are typically packaged in a semiconductor package that includes terminals for electrically and often mechanically connecting the semiconductor package to an external device, such as a printed circuit board. A substrate typically provides connections from electrical connections of the semiconductor die (via wire-bonding to pads or ball-attach) to the terminals by providing a circuit pattern in or on the surfaces of one or more dielectric layers. When multiple layers are incorporated in the substrate, vias provide connections between layers.
As semiconductor die circuit complexity has increased, the number of electrical connections has generally increased, causing a need for increasingly dense terminal arrays. The substrate circuit density generally limits the terminal density, as the line width, inter-line spacing and via size of the substrate circuit pattern dictate the density of the terminal pattern. With techniques such as laminated circuit patterns, and dielectric-embedded circuit patterns, substrate conductor density can be increased dramatically. However, the minimum via diameter still provides a limitation on either the number of terminals (due to deletion of terminals in via areas) or the terminal spacing (due to the presence of vias between terminals). The minimum via diameter is dictated by several factors, including registration between layer circuit patterns, plating or etching tolerances and photo-mask tolerance and alignment limitations.
In particular, a via will not plate properly when the circuit pattern is large compared to the via. Because the height of the via requires substantial upward plating, the via must be of sufficient diameter to permit the growth of the via, while providing an efficient plating process for the balance of the circuit pattern. Further, when a via is formed through the substrate dielectric material, the material is laser-ablated or otherwise drilled through to provide the via hole. The depth of the via hole dictates the process time required to laser-ablate the hole.
Therefore, it would be desirable to provide substrates having reduced via diameter in light of the above-listed limitations and while providing a desirable plating aspect ratio. It would further be desirable to provide a method of manufacturing the substrates having decreased via diameter with low incremental cost. It would also be desirable to reduce the time required to generate via holes in a dielectric material.